Looking For A Dataset On RTL Timing Analysis & Combinational Complexity Prediction

I’m working on a project where I aim to develop an AI model to predict combinational complexity and signal depth in RTL designs. The goal is to quickly identify potential timing violations without running a full synthesis by leveraging machine learning on RTL characteristics.

I’m looking for a dataset that includes: • RTL designs (Verilog/VHDL) • Synthesis reports with logic depth, critical path delay, gate count, and timing information • Netlist representations with signal dependencies (if available) • Any metadata linking RTL structures to synthesis results

If anyone knows of public datasets, academic sources, or industry benchmarks that could be useful, I’d greatly appreciate it!Thanks in advance!