{"id":32766,"date":"2025-02-23T08:29:02","date_gmt":"2025-02-23T07:29:02","guid":{"rendered":"https:\/\/www.graviton.at\/letterswaplibrary\/looking-for-a-dataset-on-rtl-timing-analysis-combinational-complexity-prediction\/"},"modified":"2025-02-23T08:29:02","modified_gmt":"2025-02-23T07:29:02","slug":"looking-for-a-dataset-on-rtl-timing-analysis-combinational-complexity-prediction","status":"publish","type":"post","link":"https:\/\/www.graviton.at\/letterswaplibrary\/looking-for-a-dataset-on-rtl-timing-analysis-combinational-complexity-prediction\/","title":{"rendered":"Looking For A Dataset On RTL Timing Analysis & Combinational Complexity Prediction"},"content":{"rendered":"

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I\u2019m working on a project where I aim to develop an AI model to predict combinational complexity and signal depth in RTL designs. The goal is to quickly identify potential timing violations without running a full synthesis by leveraging machine learning on RTL characteristics.<\/p>\n

I\u2019m looking for a dataset that includes: \u2022 RTL designs (Verilog\/VHDL) \u2022 Synthesis reports with logic depth, critical path delay, gate count, and timing information \u2022 Netlist representations with signal dependencies (if available) \u2022 Any metadata linking RTL structures to synthesis results<\/p>\n

If anyone knows of public datasets, academic sources, or industry benchmarks that could be useful, I\u2019d greatly appreciate it!Thanks in advance!<\/p>\n<\/div>\n

submitted by \/u\/Kafkaa24 <\/a>
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